SystemVerilog provides two constructs to declare random variables rand and randc. Variables declared with the rand keyword are normally randomized, and their values are uniformly distributed. A randc variable, on the other hand, gets randomized in a cyclic fashion. When a randc variable is randomized multiple times, the randomization engine would exhaust all the values in it’s range without making any repetition. When all the possible values get exhausted, the randomization engine resets the cycle and starts all over again.
Cyclic randomization is often used by verification engineers to accelerate meeting functional coverage goals. It is almost always a bad idea. So much so, that we decided to completely drop randc in eUVM. In this week’s blog post, we consider the pitfalls of randc, and the alternative ways to implement the behavior when you particularly need it.
First off, most verification engineers miss the finer implementation details when they add a randc variable in UVM transaction. Note that the normal UVM sequence flow is create an item and then randomize it before it is sent to the driver.
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class foo extends uvm_sequence_item;
endclass