Testbench is a Software

Whether the testbench is coded in Systemverilog or in SystemC/C++ or Specman-e, one thing remains consistent -- A Testbench is a Software.

Not surprisingly, all decent verification methodologies including UVM/OVM and VMM, are based on Object Oriented design principles. Transaction objects are generated using abstract factories pattern. And callbacks are nothing but an implementation of the Observer Pattern.

At Coverify, we build testbenches using sound principles of Object Oriented Programming. Do have a look at our Open Source VIP portifolio (coming up soon)!

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But it is Hardware that we verify

Since Hardware Designs are what we verify, verification has to be hardware centric.

And while you are here, do check our SystemVerilog Wiki -- which aims to become a community site with consolidated information on SystemVerilog language, and related tools and methodologies.

• The SystemVerilog Wiki

Modeling Algorithms

From dynamic arrays to deques, SystemVerilog is a replica of C++ standard library when it comes to data-structures. But what about algorithms?

There are two reasons why at CoVerify, we have come to rely on C++ for implementing algorithms. Firstly, C++ has thousands of these algorithms implemented in form of free libraries available as open source.

Secondly, by using C++ for implementing verification model, one can avoid making same mistakes as in design. If SystemVerilog is used for both design and verification model, the designer and the verification engineer are far more likely to use the same/similar procedures, thus avoiding and committing the same set of errors.

• The CoVerification Blog

Electronic System Level

Love it or hate it, you can no longer ignore SystemC.

There is no alternative to C/C++, when it comes to embedded software programming. For this reason, SystemC rules when it comes to coverification.

Do check how Emacs and Vim macros available at our site can help you conquer SystemC verbosity.

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And finally you need a script!

However much you may come to rely on the standard methodology libraries, you will need customisation. And you will need automation.

And this is where you need a scripting language. For, can you parse an XML file in SystemVerilog?

Do check out our boost::python based scripting interface to Verilog PLI (VPI) and the upcoming VHDL interface standard (VHPI).

• The CoVerification Blog